Integrated semiconductor circuits are built through a very intricate process of creating and interconnecting, on a silicon wafer, a plurality of devices comprised of layers of chemicals with various electromechanical properties. The steps for producing such devices are discussed herein as background for the discussion of the invention.
The process begins with a silicon wafer and the designation of doped moat areas, where NMOS and PMOS devices are to be created. The moat regions that will support PMOS devices are n-doped, and the moat regions that will support NMOS devices are p-doped. NMOS and PMOS regions must be electrically isolated in order to prevent unintended conductivity. This isolation is implemented by forming an isolation structure between these regions, comprising a trench etched between the regions and filled with a dielectric material.
Following formation of the isolation trench, a layer of controllably conductive material is selectively deposited to form the gate regions of transistors in each moat, where each gate connects two active transistor areas. These active transistor areas are doped accordingly: the active transistor areas of NMOS devices are n-doped, and the active transistor areas of PMOS devices are p-doped, such that the active transistor areas are isolated by the inversely doped moat region.
Finally, a layer of dielectric is deposited atop the wafer and manufactured devices in order to protect and electrically insulate the devices. Contact vias are selectively etched through the dielectric material in order to provide access to each gate and active transistor area; these contact vias are filled with one or more conductive metals, and the surface contact points for each metallized contact via are interconnected to produce a fully interconnected integrated circuit.
Several steps in this process involve the formation of a layer only in desired regions of the semiconductor. Selective deposition involves the deposition of the layer material across the entire surface of the semiconductor, followed by the selective removal of the layer material from undesired regions. This selective removal is often performed by a photolithography process. This process begins by forming a layer of photoresist material, which is sensitive to ultraviolet light, atop the layer to be selectively removed. A photolithography mask is prepared, which contains a series of transparent regions corresponding to regions of undesired material, and opaque regions corresponding to regions of desired material. This photolithography mask is positioned over the photoresist layer, and ultraviolet light is directed toward the photolithography mask, such that the exposed regions of photoresist are selectively softened. The semiconductor is then exposed to a developer solution that selectively washes away the softened photoresist material, while leaving behind the unsoftened photoresist regions. This process selectively exposes regions of the underlying layer, which can be selectively removed by exposing the semiconductor to an etching solution that is chemically selective for the material of the underlying layer. Finally, the remaining photoresist material is removed, usually by an ashing process. The result of this photolithography process is a selectively deposited layer upon the semiconductor.
A common problem with this selective deposition technique is the risk of unintentionally etching the materials and layers underneath the layer that is being selectively etched. This may occur if the underlying material is sensitive to the etching solution used for etching the selectively deposited layer atop it; in this case, the underlying layer may be unintentionally etched during the etching step. Accordingly, prior to forming any layer that is to be selectively deposited, it is often advantageous to form an “etch-stop” layer that is less sensitive to the etching solution than the material of the selectively deposited layer. This etch-stop layer protects the underlying materials from unintended exposure to the etch solution, while permitting a completion of the etching of the selectively deposited layer. In many cases, the fabrication process may intentionally expose the selectively deposited layer to etching solution for longer than necessary, in order to guarantee full etching of all undesired areas of this layer across the entire semiconductor surface. This “over-etching” step is only feasible because the comparative insensitivity of the etch-stop layer to the etching solution protects the underlying materials from unintended exposure to the etching solution.
In some instances, multiple etch-stop layers are required to protect against unintended etching during multiple etching steps. One example where multiple etch-stop layers are required is during the formation of the isolation trench. The isolation trench is formed in several steps, which are illustrated in FIGS. 1A-1G.
The process begins with the provision of a silicon wafer 2. In the first step, shown in FIG. 1A, an oxide liner layer 4 is formed atop the silicon substrate 6; this is often performed by exposing the silicon to heat and oxygen, thereby creating a silicon oxide layer across the entire silicon wafer. Next, as shown in FIG. 1B, an active region liner layer 8 is deposited atop the silicon oxide layer 4, which serves as a second liner layer. A common choice of material for this layer is dichlorosilane (DCS) nitride, which may be deposited by chemical vapor deposition (CVD), sputtering, etc. In the third step, shown in FIG. 1C, the active region liner layer 8, oxide liner layer 4, and silicon substrate 6 are selectively removed from the area where an isolation trench is to be formed 14. This selective removal is performed by forming a photoresist layer 10 atop the active region liner layer 8; selectively softening the photoresist layer atop the isolation trench area 14 through the use of a photolithography mask and exposure of undesired regions to ultraviolet light (not shown); and selectively removing the softened photoresist material via a developer solution (not shown). The result of this step is the selective exposure of the active region liner layer 8, silicon oxide 4, and silicon substrate 6 in the isolation area. Subsequent exposure of the semiconductor 2 to a trench etch solution 12 removes these materials in the isolation area, thereby creating an isolation trench 14.
In the next step, shown in FIG. 1D, the remaining photoresist material 10 is removed via ashing, and the isolation trench 14 is lined with a trench liner layer 16. The material conventionally chosen for the trench liner layer 16 is the same DCS nitride that comprises the active region liner 8.
In the next step, shown in FIG. 1E, a layer of dielectric material 18 is formed over the surface of the semiconductor 2, including within the isolation trench 14. In the next step, shown in FIG. 1F, the semiconductor 2 is subjected to a planarization process 22, such as chemical mechanical polishing (CMP), to remove the upper layers of the semiconductor. In the active region, this planarization 22 removes both the dielectric material 18 and the trench liner layer 16, thereby exposing the active region liner layer 8 formed on the silicon oxide liner 4. In the isolation trench 14, this planing 22 leaves behind the dielectric material 18 and the trench liner layer 16.
In the next step, shown in FIG. 1F, the semiconductor 2 is exposed to an etching solution that is specific to the material comprising the active region liner 8. Hot phosphoric acid is often chosen as the etch solution in this step due to its high selectivity for DCS nitride. During the nitride layer etch 22, the DCS nitride 8 is removed from the active region, while the trench is protected from etching by the dielectric material 18. The resulting semiconductor substrate presents active regions coated with silicon oxide 4, separated from adjacent active regions by an isolation trench 14 filled with dielectric material 18.
An additional feature of transistors manufactured in this manner is related to the performance of transistors. An additional and desirable property of such transistors is mechanical stress, in the form of tensile or compressive strain, which increases the mobility of the carrier (electrons or electron deficits) through the transistor. This increased carrier mobility may translate to faster switching speeds of the transistor and/or operation at lower voltages. For NMOS devices embedded in an active region, the effect is optimal if a tensile stress is exerted on the active region.
Contemporary methods incorporate this feature by including a nitride film layer in the isolation trench. Prior to the deposition of dielectric material in the isolation trench, a nitride layer is deposited within the isolation channel. The nitride layer may be formed by any appropriate method, e.g., chemical vapor deposition (CVD) or sputter deposition. Subsequent thermal processing of this layer creates a tensile strain on the moat in the range of 400-600 MPa. However, a greater tensile strain would further improve the performance of the transistor.
It is always desirable to make further improvements in isolation structures and fabrication techniques.